1. Field of the Invention
The present invention relates to a semiconductor-device isolation structure, and more particularly, to a manufacturing method for preventing contact etch stop layers from having seams or voids, so that short-circuiting between contact plugs formed in the following process can be avoided.
2. Description of the Prior Art
Traditional field oxide (FOX) structures applied to isolate the semiconductor devices are formed by a method of local oxidation of silicon (LOCOS). However, the isolating method of LOCOS has several disadvantages of lateral growth of the field oxide, lateral diffusion of field doping ions, thinning effect in small-sized field oxide and bird's beak, so shallow trench isolation (STI) structures are developed to manufacture the deep sub-micron integrated circuit. The processes of forming the STI structure are described as follows. First, a trench is formed in the semiconductor substrate. Then, the trench is filled with an insulating material, and the insulating material is planarized to be the insulating region used for isolation, so that the bird's beak of the LOCOS will not occur. The STI structure has advantages of small isolation line width, explicit division of active regions, uniform depth of isolation regions, scalable size and excellent planar structure of isolation regions so as to become a preferably ideal isolation technology at present. Therefore, the STI structure is widely applied to manufacture the integrated circuits in 0.25 micron.
Referring to FIG. 1 and FIG. 2, FIG. 1 is a top view illustrating a layout of a semiconductor device, such as DRAM, according to the prior art, and FIG. 2 is a cross-sectional view illustrating a semiconductor-device isolation structure shown in FIG. 1 along a line AA′. As shown in FIG. 1, in the processes of forming each transistor of a memory cell, first, at least one STI structure 102 is formed on the substrate 100, and the STI structure 102 defines a plurality of active regions 104. Each active region 104 is isolated from the other adjacent active regions 104 by the STI structure 102. Next, a plurality of gate structures 106 are formed on each active region 104 and the STI structure 102, and then, spacers 108 are respectively formed on the sidewall of each gate structure 106. Next, a self-aligned silicide (salicide) process is performed to form corresponding silicide layers respectively disposed on each gate structure 106 and each active region 104.
However, during the manufacturing processes of the semiconductor device according to the prior art, the etching process and the cleaning process, such as an etching process for removing a cap layer and a hard mask layer on each transistor, an etching process for forming spacers 108, a pre-cleaning process performed after the etching process for forming the spacers 108, a cleaning process performed after forming the source electrode/drain electrode in the active region 104, a pre-cleaning process performed before forming the silicide layers, and an etching process for removing metal layers without reacting, are performed several times. During the etching processes and the cleaning processes, the exposed STI structure 102 is damaged by the etching processes and the cleaning processes so as to form recesses 110, which possibly have depths about several hundred angstroms or more, disposed on the surface of the STI structure 102 between any of two adjacent gate structures 106, as shown in FIG. 2. Because the isotropic etching processes and the cleaning processes, especially the pre-cleaning process before the salicide process and the etching process after the salicide process, cause deep and lateral corrosion for the STI structures 102, the recesses 110 are enlarged to be under the spacers 108 or even under the gate structures 106 so as to cause the leakage current in the device.
In addition, because a method for reducing the size of the device to raise the performance of a metal-oxide-semiconductor field-effect transistor (MOSFET) also suffers from limits of technology and expensive cost in the photolithographic process, most of the current semiconductor processes utilize a strained-Si channel technology, such as utilizing a contact etch stop layer (CESL) with compressed/strained stress, to raise mobility of carriers so as to increase driving current of the device. Referring to FIG. 3, FIG. 3 is a cross-sectional view illustrating the semiconductor-device isolation structure shown in FIG. 2 further having the CESL formed thereon. As shown in FIG. 3, in the following process used to form a CESL 112, due to the recesses 110 on the surface of the STI structure 102 and the tightness between each gate structure 106, a chemical vapor deposition (CVD) process used to deposit the CESL 112 easily causes an effect of overhang. For this reason, the CESL 112 covering the substrate 100 and filling the recesses 110 has the overhangs at openings of the recesses 110, and a portion of the overhangs even connect to each other so as to have seams or voids 114.
Next, in the following process, the CESL is covered with an inter-layer dielectric (ILD) layer, and then, corresponding contact windows are respectively formed on the gate electrode and the source-electrode/drain-electrode doping region of each transistor. Thereafter, the contact windows are filled with tungsten to form tungsten plugs. Because the seams or voids in the CESL on the STI structure and the great gap-fill ability of tungsten in the CVD process of tungsten, tungsten will fill the seams or voids of the CESL in the process of forming the tungsten plugs. Therefore, adjacent tungsten plugs have a contact bridge so as to connect to each other, so the integrated circuits cannot regularly operate.